Semicon India - Future Design
Second Road Show: Design Linked Incentive (DLI) Scheme
Date: Feb 24, 2023
Venue: J N Tata Auditorium, IISc, Bengaluru
About Semicon India: The GOI has come out with National Policy on Electronics- 2019 that aims to position India as a global hub for Electronics System Design and Manufacturing (ESDM) and envisions creation of a vibrant semiconductor chip design ecosystem in the country. With abundance of design engineers available in India, making India a Global hub for Chip Manufacturing and related hardware design is the goal of Indian Semiconductor Mission (ISM) as proposed by GOI. A series of roadshows are being organized by MeitY across the country to create awareness among Young Engineers and Entrepreneurs towards Semiconductor Design. This is a part of Make in India – Design in India programme.
About DLI Scheme: Ministry of Electronics and Information technology (MeitY) has announced the SemiconIndia: FutureDesign - Design Linked Incentive (DLI) Scheme to encourage & support domestic industry involved in semiconductor design and promote start-ups in Chip design/IP design/Fab etc. The Chip-IN centre at CDAC (Centre for Development of Advanced Computing), Bengaluru, is the nodal agency, for implementing DLI scheme and acts as a single-window system to facilitate start-ups with the process, prototyping lab.
Highlights of Roadshow:
i. Stimulate the next-gen Semiconductor Designers
ii. Promote the culture of Co-development and joint ownership of IPs with active industry participation
iii. Indigenously Develop Semiconductor Chips for Automobile, Mobility, Communication & Computing.
About the Event: The event at IISc was inaugurated by Hon’ble Rajeev Chandrashekhar, MoS, MeitY and Skill Development, GOI, along with other dignitaries from Industry. During his speech, the Minister highlighted the special emphasis given by GOI towards Semiconductor Industry and urged budding Engineers and Entrepreneurs to make India the Semiconductor hub for the world. He also said, a special B.Tech curriculum in VLSI design is planned from 2023-24 to create the talent pool.
The first batch of beneficiaries of DLI scheme: Mr. Rakesh Malik- CEO & Founder, VerveSemi Microelectronics, Mr. Gautam Singh- CEO & Founder, Fermionic Design and Ms. Vrinda Kapoor, COO, DV2JS Innovation, were felicitated by the Minister.
Panel discussions including Industry majors, Academicians and start-up entrepreneurs were held to discuss the challenges and opportunities in Chip design area and to facilitate Capital funding for start-ups.
Many eminent persons like Mr. Sailesh Chittipeddi - Renesas Electronics, Mr. Anand Ramamoorthy-Micron, Prof. Kamakoti- IIT Madras, Mr. Naveed Sherwani - Rapid Silicon, Mr. Ruchir Dixit – Siemens EDA, Mr. Rama Bethmangalkar-Qualcomm Ventures, Som Pal Choudhary- Bharat Invocation Fund, Mr. Raja Subramaniam -Synopsys, Mr. Ajay Pratap Singh, Cadence Design Systems and many others participated in the Panel discussion and Q&A sessions.